1. Field of the Invention
The present invention relates to SOI (Semiconductor On Insulator) structure MIS (Metal Insulator Semiconductor) type FET (Field Effect Transistor, hereinafter such a transistor is referred to as SOIMISFET). The invention relates particularly to a technique of fixing the body potential of the SOIMISFET.
2. Description of the Background Art
FIG. 41 is a sectional view showing the structure of a conventional SOIMISFET. An insulator 82 is formed on the entire surface of a substrate 81 and a semiconductor layer 90 is formed thereon. Note that the semiconductor layer 90 is sectioned by an element isolation portion 94 which is insulating and in contact with the insulator 82.
A gate insulating film 95d is selectively formed on the upper surface of the semiconductor layer 90, or on its main surface away from the contact with the insulator 82, and a gate electrode 95e is formed on the gate insulating film 95d; the gate electrode 95e faces the upper surface of the semiconductor layer 90 through the gate insulating film 95d. The gate insulating film 95d and the gate electrode 95e form a gate structure 95.
A pair of impurity regions, or a drain 91 and a source 92, are formed to the upper surface of the semiconductor layer 90 from its lower surface or main surface in contact with the insulator 82. The drain 91 and the source 92 somewhat penetrate under the ends of the gate insulating film 95d and face each other through the body 90a, i.e. the semiconductor layer 90 under the gate insulating film 95d. For example, with an n-type SOIMISFET, the drain 91 and the source 92 are set to n+ type and the body 90a is set to pxe2x88x92 type.
The conventional SOIMISFET had the problem that the body 90a is in a floating state, which causes parasitic bipolar phenomenon and reduces the breakdown voltage between the source 92 and the drain 91. This problem is described on and after page 426 in IEEE Trans. on Electron Devices Vol. 35, no. 4, April 1988 by K. K. Young, et al., for example.
This problem will now be briefly described with an n-type SOIMISFET. A passage of current between the source 92 and the drain 91 causes impact ionization in the drain 91. Then holes take place and are accumulated in the body 90a in a floating state, which increases the potential at the body 90a. The potential rise in the body 90a turns on the npn-type parasitic bipolar transistor formed by the source 92, body 90a and drain 91, which causes feedback in which the current flowing between the source 92 and drain 91 increases. This deteriorates the breakdown voltage between the source 92 and drain 91.
Furthermore, the floating-state body 90a also causes so-called 1/f noise due to the potential instability. This problem is described on and after page 99 in Y.-C. Tseng, et al. 1997 Symp. On VLSI Tech. Digest of Technical Paper, for example. The structure shown in FIG. 41 has been regarded as unsuited for high-frequency analog devices because of the presence of the noise.
Meanwhile, SOIMISFETs having body potential drawing portions and ring-like gate structures have been suggested to avoid the floating state of the body 90a so as to improve the high-frequency characteristics, an example of which is shown in Japanese Patent Laying-Open No. 10-214971.
FIG. 42 is a plan showing the structure of an SOIMISFET having a ring-like gate structure; the section seen from the direction indicated by the arrows MM in the diagram corresponds to the sectional view of FIG. 41.
In the plane view, the gate structure 95 has an octagonal closed-loop portion and a pair of extensions 96 each coupled to the closed-loop portion and to contact pad 97. The drain 91 is surrounded by the closed-loop portion. Two pairs of sources 92 are provided outside the closed-loop portion; the sources 92 in each pair adjoin with an extension 96 therebetween. Body potential drawing portions 93 are each interposed between two sources 92 belonging to different pairs. The body potential fixing portions 93 are set to a different conductivity type from the drain 91 and the sources 92; for example, they are set to p+-type in an n-type SOIMISFET.
The sources 92 and the body potential fixing portions 93 are surrounded by the element isolation portion 94. The gate contact pads 97, the drain 91, the sources 92, and the body potential fixing portions 93 have contacts 97c, 91c, 92c and 93c, respectively.
In the structure shown in FIG. 42, formation of the sources 92 and the body potential fixing portions 93 of different conductivity types requires ion implantation to be separately applied inside and outside the boundaries shown by the broken line. However, in practice, ions of different conductivity types do not always exclusively exist in the vicinity of the boundaries. When silicon is adopted as the semiconductor, cobalt silicide etc. is often formed on the boundaries between the sources 92 and the body potential fixing portions 93. However, it is not easy to favorably perform the silicidation in areas where ions of different conductivity types are mixed. Even if the growth can be achieved, it may peel off.
Further, in the structure shown in FIG. 42, it is not desirable to apply the so-called partial trench isolation. FIG. 44 is a sectional view showing a problem encountered when the partial trench isolation is applied to the structure shown in FIG. 42. This diagram shows an example in which the gate structure 95 has sidewalls. In the partial trench isolation, isolation oxide films 98 are provided on the upper surface of the semiconductor layer 90 without making contact with the insulator 82. The body 90a is connected to the semiconductor layer 90b under the isolation oxide film 98 on the right in the drawing through the source 92, and is further connected to the body potential fixing portion 93 through the semiconductor layer 90b. 
This structure allows the ion implantation to be separately performed on the two sides of the isolation oxide film 98 to form the source 92 and the body potential fixing portion 93 of different conductivity types, and then it is possible to avoid formation of semiconductor region in which ions of different conductivity types are mixed. However, the source 92 form the pn junction J1 with the body 90a and the pn junction J2 with the semiconductor layer 90b. Since the pn junctions J1 and J2 are series-connected with opposite polarities in the path from the body 90a to the body potential fixing portion 93, it is difficult to externally fix the potential in the body 90a via the body potential fixing portion 93.
Referring to FIG. 42 again, the structure can provide more favorable high-frequency characteristics as the extensions 96 are formed shorter. FIG. 43 is a circuit diagram showing an example of an equivalent circuit of the SOIMISFET. When this circuit is adopted, the maximum oscillation frequency fmax of the transistor can be given with the cur-off frequency fT as follows.                                                                         f                max                            =                                                f                  T                                                  2                  ⁢                                                                                                              R                          g                                                ⁡                                                  (                                                                                    g                              ds                                                        +                                                          2                              ⁢                                                              xe2x80x83                                                            ⁢                              π                              ⁢                                                              xe2x80x83                                                            ⁢                                                              f                                T                                                            ⁢                                                              C                                gd                                                                                                              )                                                                    +                                                                        g                          ds                                                ⁡                                                  (                                                                                    R                              i                                                        +                                                          R                              s                                                                                )                                                                                                                                                                                                            f                T                            =                                                g                  m                                                  2                  ⁢                                      xe2x80x83                                    ⁢                  π                  ⁢                                      xe2x80x83                                    ⁢                                      (                                                                  C                        gs                                            +                                              C                        gd                                                              )                                                                                                          Eq        .                  xe2x80x83                ⁢        1            
Where Ri, Rg, Rs, Rd and Rds, are body resistance, gate resistance, source resistance, drain resistance and drain-source resistance, Cgs, Cds, and Cgd are gate-source capacitance, drain-source capacitance and gate-drain capacitance, and gm and gds are transconductance and drain conductance, respectively.
The minimum noise figure Fmin can be given as follows.                                                                         F                min                            =                              xe2x80x83                            ⁢                              1                +                                  2                  ⁢                                      xe2x80x83                                    ⁢                  π                  ⁢                                      xe2x80x83                                    ⁢                                      fKC                    gs                                    ⁢                                                                                                              R                          g                                                +                                                  R                          s                                                                                            g                        m                                                                                                                                                                    k              ≈                              xe2x80x83                            ⁢              2.5                                                          Eq        .                  xe2x80x83                ⁢        2            
As can be seen from the two equations above, decreasing the gate resistance Rg improves the maximum oscillation frequency fmax and the minimum noise figure Fmin.
According to a first aspect of the present invention, a semiconductor device comprises: an insulating layer having a main surface extending in a first direction and a second direction which intersect with each other; a semiconductor layer having a first conductivity type and having a first main surface and a second main surface which is in contact with the main surface of the insulating layer; at least one element isolation portion which is insulative and formed on the first main surface apart from the second main surface; at least one body potential fixing portion having the first conductivity type, formed at least on the first main surface of the semiconductor layer, and in contact with a first under semiconductor layer which is the semiconductor layer existing between the element isolation portion and the second main surface; at least one gate structure in which a gate insulating film is formed on the first main surface and a gate electrode is formed over the first main surface with the gate insulating film interposed therebetween, the at least one gate structure comprising a closed-loop portion which crosses a boundary between the element isolation portion and the first main surface and forms a closed loop on the element isolation portion and the first main surface, the closed loop being kept away from the body potential fixing portion; at least one first impurity region having a second conductivity type which is opposite to the first conductivity type, formed from the first main surface to the second main surface, and surrounded by the first under semiconductor layer and a second under semiconductor layer which is the semiconductor layer existing between the gate structure and the second main surface; and at least one second impurity region having the second conductivity type, facing to the first impurity region through the second under semiconductor layer, and separated from the body potential fixing portion by the first under semiconductor layer.
Preferably, according to a second aspect of the invention, in the semiconductor device, the first and second impurity regions are a drain and a source, respectively.
Preferably, according to a third aspect of the invention, in the semiconductor device, a plurality of first impurity regions and/or a plurality of second impurity regions are provided, and the first impurity region and the second impurity region are alternately arranged around one element isolation portion.
Preferably, according to a fourth aspect of the invention, in the semiconductor device, a plurality of element isolation portions are provided, one gate structure is provided over the plurality of element isolation portions, and the gate structure has gate contact pads on the element isolation portions.
Preferably, according to a fifth aspect of the invention, in the semiconductor device, a plurality of body potential fixing portions are provided, one body potential fixing portion is surrounded by one element isolation portion, and the element isolation portions are arranged checkerwise and the one gate structure has the gate contact pads on two of the element isolation portions.
Preferably, according to a sixth aspect of the invention, in the semiconductor device, a plurality of gate structures are provided, and the element isolation portions are arranged in a matrix and the one gate structure has the gate contact pads on four of the element isolation portions.
Preferably, according to a seventh aspect of the invention, in the semiconductor device, the body potential fixing portion is adjacent also to the second under semiconductor layer.
According to an eighth aspect of the invention, a semiconductor device comprises: an insulating layer having a main surface extending in a first direction and a second direction which intersect with each other; a semiconductor layer having a first conductivity type and having a first main surface and a second main surface which is in contact with the main surface of the insulating layer; at least one gate structure in which a gate insulating film is formed on the first main surface and a gate electrode is formed over the first main surface with the gate insulating film interposed therebetween, the at least one gate structure comprising a closed-loop portion forming a single closed loop and at least one extension having its one end coupled to the closed-loop portion; at least one first impurity region and at least one second impurity region both having a second conductivity type opposite to the first conductivity type and formed from the first main surface to the second main surface of the semiconductor layer, the first impurity region and the second impurity region being separated from each other by an under semiconductor layer which is the semiconductor layer existing between the closed-loop portion of the gate structure and the second main surface; and at least one body potential fixing portion having the first conductivity type and formed at least on the first main surface, the body potential fixing portion being separated from one first impurity region by the under semiconductor layer and being separated from the second impurity region by an under region located between the extension of the gate structure and the second main surface.
Preferably, according to a ninth aspect of the invention, in the semiconductor device, the first and second impurity regions are a drain and a source, respectively.
Preferably, according to a tenth aspect of the invention, in the semiconductor device, a plurality of gate structures are provided, and at least one second impurity region is interposed between a pair of body potential fixing portions.
Preferably, according to an eleventh aspect of the invention, in the semiconductor device, a plurality of gate structures are provided, and in each gate structure, the at least one extension has a contact pad at its other end, and the semiconductor device further comprises at least one element isolation portion which is insulative and provided on the first main surface and at least one of the contact pad of different ones of the gate structures are provided on the element isolation portion.
Preferably, according to a twelfth aspect of the invention, in the semiconductor device, the extensions are also provided on the element isolation portion.
Preferably, according to a thirteenth aspect of the invention, in the semiconductor device, one gate contact pad is provided on one element isolation portion and shared by different ones of the gate structures.
Preferably, according to a fourteenth aspect of the invention, in the semiconductor device, the closed-loop portions are provided in a matrix, a plurality of element isolation portions are provided, one gate structure comprises a plurality of extensions, and one element isolation portion is surrounded by a quadrilateral formed by two pairs of the gate structures, and wherein, among the extensions of the two pairs of closed-loop portions, the extensions which extend to one element isolation portion are coupled with each other at the gate contact pad, and four of the extensions of the two pairs of the closed-loop portions form the sides of the quadrilateral.
Preferably, according to a fifteenth aspect of the invention, in the semiconductor device, a plurality of second impurity regions and a plurality of body potential fixing portions are provided for one gate structure, and the second impurity regions and the body potential fixing portions are alternately arranged around one first impurity region, with a plurality of extensions interposed therebetween.
Preferably, according to a sixteenth aspect of the invention, in the semiconductor device, a plurality of second impurity regions and a plurality of body potential fixing portions are provided for one gate structure, the second impurity regions and the body potential fixing portions are arranged around one first impurity region with a plurality of the extensions interposed therebetween, and the gate contact pad which is coupled with one of the extensions interposed between a pair of the second impurity regions or a pair of the body potential fixing portions is respectively surrounded by the second impurity regions or the body potential fixing portions.
Preferably, according to a seventeenth aspect of the invention, in the semiconductor device, a boundary between the second impurity region and the closed-loop portion is longer than a boundary between the body potential fixing portion and the closed-loop portion.
Preferably, according to an eighteenth aspect of the invention, in the semiconductor device, a boundary between the body potential fixing portion and the closed-loop portion is longer than a boundary between the second impurity region and the closed-loop portion.
Preferably, according to a nineteenth aspect of the invention, in the semiconductor device, the closed-loop portion has a larger width in a position interposed between the body potential fixing portion and the first impurity region than in a position interposed between the first impurity region and the second impurity region.
According to the semiconductor device of the first aspect of the invention, the gate structure crosses a boundary between the element isolation portion and the first main surface, so that the second under semiconductor layer can be connected to the body potential fixing portion through the first under semiconductor layer. Hence, the part of the second under semiconductor layer which is interposed between the first impurity region and the second impurity region and functions as the body can be fixed at a given potential without through the pn junctions which the second under semiconductor layer forms with the first and second impurity regions.
According to the semiconductor device of the second aspect of the invention, the second impurity region formed outside of the closed-loop portion can be formed larger than the first impurity region formed inside the closed-loop portion. Then the drain current can be expanded and a larger number of source contacts can be formed, which reduces the source resistance and improves the frequency characteristic and noise characteristic.
According to the semiconductor device of the third aspect of the invention, a plurality of transistors are formed around the element isolation portion. Furthermore, the transistors can share the body potential fixing portion in common, so that the layout area can be reduced. This also enables easy layout.
According to the semiconductor device of the fourth aspect of the invention, the interval between the gate contact pads and the semiconductor layer can be made larger, which reduces the parasitic capacitance. Furthermore, since the gate structure extends over the boundaries between the element isolation portions and the first main surface, the distance between the gate contact pads on the element isolation portions and the closed-loop portion can be reduced to reduce the gate resistance. Reducing the parasitic capacitance and the gate resistance improves the high-frequency characteristic.
According to the semiconductor device of the fifth aspect of the invention, adjacent transistors share the first impurity region as drain and the second impurity regions serving as source can be easily formed in larger area.
According to the semiconductor device of the sixth aspect of the invention, an increased number of body potential fixing portions can be connected to the body, which improves the function of fixing the body potential. Further, an increased number of gate contact pads can be provided for one gate structure, which reduces the gate electrode resistance.
According to the semiconductor device of the seventh aspect of the invention, the part of the second under semiconductor layer which is interposed between the first impurity region and the second impurity region and functions as the body can be connected to the body potential fixing portion not only through the first under semiconductor layer but also through the part of the second under semiconductor layer which does not function as the body, which enables the body potential to be more efficiently fixed.
According to the semiconductor device of the eighth aspect of the invention, the under semiconductor layer between the first impurity region and the second impurity region is connected to the body potential fixing portion, so that the under semiconductor layer can be fixed at a given potential. Furthermore, the extension of the gate structure extends between the second impurity region and the body potential fixing portion of different conductivity types, so that the two regions do not directly adjoin. This enables favorable formation of metal compound on the regions.
According to the semiconductor device of the ninth aspect of the invention, the second impurity region formed outside of the closed-loop portion can be formed larger than the first impurity region formed inside the closed-loop portion. Then the drain current can be expanded and a larger number of source contacts can be formed, which reduces the source resistance and improves the frequency characteristic and noise characteristic.
While, in a semiconductor device, the second impurity region as the source and the body potential fixing portion are usually connected in common in use, different amounts of current flow in these regions. According to the semiconductor device of the tenth aspect of the invention, the magnitude of voltage drop tends to be uniform in an array of transistors, which improves the linearity of the characteristics.
According to the semiconductor device of the eleventh aspect of the invention, the interval between the gate contact pads and the semiconductor layer can be enlarged, which reduces the parasitic capacitance.
According to the semiconductor device of the twelfth aspect of the invention, the interval between the extensions and the semiconductor layer can be enlarged to suppress the parasitic capacitance.
According to the semiconductor device of the thirteenth aspect of the invention, the number and area of the gate contact pads can be reduced to reduce the parasitic capacitance of the gate structure, and the area of the element isolation portion can be reduced to enhance the degree of integration of the semiconductor device.
According to the semiconductor device of the fourteenth aspect of the invention, not only the closed-loop portions but also the element isolation portions can be arranged in a matrix, which reduces the area required for the layout.
According to the semiconductor device of the fifteenth aspect of the invention, a plurality of transistors sharing the first impurity region as the drain can be formed to reduce the layout area. Furthermore, the layout is easy and the overall non-uniformity of the amount of current can be suppressed.
According to the semiconductor device of the sixteenth aspect of the invention, even if the second impurity regions as the source and the body potential fixing portions arranged around the first impurity region as the drain display inferior symmetry, the second impurity regions and the body potential fixing portions arranged around the gate contact pad display improved symmetry. This suppresses the overall non-uniformity of the amount of current.
According to the semiconductor device of the seventeenth aspect of the invention, transistors with higher current driving capability can be obtained because the channel width of the transistor can be made larger as the length of the boundary between the second impurity region as the source and the closed-loop portion is made longer.
According to the semiconductor device of the eighteenth aspect of the invention, the body potential can be fixed more certainly because the contact area with the under semiconductor layer as the body can be made larger as the boundary between the body potential fixing portion and the closed-loop portion is made longer.
According to the semiconductor device of the nineteenth aspect of the invention, reducing the width of the closed-loop portion between the second impurity region as the source and the first impurity region as the drain shortens the channel length of the transistor, which provides the transistor with higher current driving capability. On the other hand, enlarging the width of the closed-loop portion between the body potential fixing portion and the first impurity region lengthens the interval between these regions having different conductivity types. This ensures larger margin in the process of separately introducing impurities, which enables favorable formation of metal compound on these regions.
The present invention has been made in consideration of the above-described conditions, and an object of the invention is to provide a technique for obtaining a semiconductor in which the body potential can be externally fixed with a body potential fixing portion and in which no semiconductor region exists where ions of different conductivity types are mixed.
Another object of the invention is to provide a semiconductor device with reduced gate resistance.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.